PIC16F886-I/ML【PDF 14/16 页】IC PIC MCU FLASH 8KX14 28QFN

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Sheet目录3873

10页 11页 12页 13页 [14页]15页 16页

2009 Microchip Technology Inc.

DS80302F-page 7

PIC16F88X

Module: MSSP (I2C Master Mode)

When the MSSP is I2C Master mode with a

slave device stretching the clock, the clock

generation does not function as described in the

data sheet.

When a slave device is performing clock stretching

by pulling the SCL line low, the master device

should continuously sample the SCL line to

determine when all slaves have released SCL.

When SCL is released, the master device should

wait one BRG period to ensure a constant SCL

high time.

The current implementation does not ensure

accurate SCL high time. During clock stretch, the

MSSP device will erroneously continue running

the BRG counter. At the end of the clock stretch

the BRG counter continues to count down for the

remainder of the BRG period, and then the MSSP

device will immediately resume transmitting the

data.

Figure 1 illustrates an expected I2C transmission

in which the SCL line is completely controlled by

the master device and the slave device does not

attempt to stretch the clock period.

Figure 2 illustrates the expected operation of an

I2C transmission in which the slave device has

stretched the clock period by holding the SCL line

low. The high time of the SCL pulse is constant,

regardless of the duration of the clock stretch.

Figure 3 and Figure 4 illustrate an actual I2C

transmission in which the slave has stretched the

clock period by holding the SCL line low. Note that

the high time of the SCL signal has shortened from

the expected time.

FIGURE 1:

ACTUAL (CORRECT) OPERATION WITHOUT CLOCK STRETCHING

FIGURE 2:

EXPECTED OPERATION WITH CLOCK STRETCHING

BRG Period

SDA

SCL

Master

Slave

BRG Period

SDA

SCL

Master

Slave

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